With shrinking dimensions of various integrated circuit components, transistors such as FETs have experienced dramatic improvements in both performance and power consumption. These improvements may be largely attributed to the reduction in dimensions of components used therein, which in general translate into reduced capacitance, resistance, and increased through-put current from the transistors.
Nevertheless, performance improvement brought up by this type of “classic” scaling, in device dimensions, has recently met obstacles and in some cases even been challenged, when the scaling goes beyond a certain point, by the increase in leakage current and variability that are inevitably associated with the continued reduction in device dimensions. Planar transistors, such as metal oxide semiconductor field effect transistors (MOSFETs) are particularly well suited for use in high-density integrated circuits. As the size of MOSFETs and other devices decreases, the dimensions of source/drain regions, channel regions, and gate electrodes of the devices, also decrease.
Moreover, extremely thin SOI (ETSOI) devices have been pursued as device architecture for continued CMOS scaling. To render ETSOI a true technology, on-chip capacitor is needed along with ETSOI CMOS transistors for a variety of applications such as system-on-chip (SoC) application.
Silicon-on-insulator (SOI) technology allows the formation of high-speed, shallow junction devices. In addition, SOI devices improve performance by reducing parasitic junction capacitance. In an SOI substrate, a buried oxide (BOX) film made of silicon oxide is formed on single crystal silicon, and a single crystal silicon thin film is formed thereon. Various methods of fabricating such SOI substrates are known, one of which is Separation-by-Implanted Oxygen (SIMOX) process, wherein oxygen ions are implanted into a silicon substrate at a desired depth to form a BOX film. The substrate is then annealed at high temperature, typically 1300° C. and an inert ambient with a small amount of oxygen, so that the oxygen-implanted region of the substrate is converted into silicon oxide. Another method of forming an SOI substrate is wafer bonding, wherein two semiconductor substrates with silicon oxide surface layers are bonded together at the silicon oxide surfaces to form a BOX layer between the two semiconductor substrates, followed by thinning ETSOI, a fully depleted device uses an ultra-thin silicon channel wherein the majority carriers are fully depleted (FD) during operation.
Referring to FIG. 1, there is shown a prior art illustrative structure of an FET device on a semiconductor-on-insulator (SOI) substrate are described having an extremely thin semiconductor-on-insulator (ETSOI) layer. The (ETSOI) layer is present atop the buried insulating layer of an SOI substrate, the ETSOI layer having a thickness preferably ranging from 3 nm to 20 nm. The raised source regions and raised drain regions are formed on an upper surface of ETSOI layer in which the semiconductor is present, preferably formed using an epitaxial deposition process.
Due to the high resistance of the undoped extremely thin SOI body, prior ETSOI capacitors suffer from a high body resistance resulting in poor quality. To render ETSOI a true technology, there is a need in industry for a high quality on-chip capacitor integrated with ETSOI CMOS transistors for a variety of applications such as system-on-chip (SoC) application.